1. Field of the Invention
The present invention relates to a broadband parallel power amplification apparatus, and more particularly, to a power amplification apparatus in which output matching impedance transformation rates are equalized and a quarter-wave circuit and a delay compensation circuit are included in input/output matching circuits to be advantageous for operation in a broadband frequency.
2. Description of the Related Art
As is generally known in the art, recently, research has been conducted to improve the efficiency of a mobile communication terminal. In particular, research for a Doherty power amplifier capable of improving efficiency has been actively conducted.
The Doherty power amplifier is devised by W. K. Doherty in 1936. In the Doherty power amplifier, a carrier amplifier and a peaking amplifier are connected in parallel. The output load impedance of the carrier amplifier is controlled by changing the amount of current flowing through the peaking amplifier according to an output power level to improve efficiency.
Hereafter, a conventional power amplification apparatus will be described with reference to the attaching drawing.
FIG. 1 is a circuit diagram showing an exemplary Doherty power amplification apparatus among conventional power amplification apparatuses. The power amplification apparatus includes an input divider 11, a delay compensation circuit 12, input matching circuits 13 of carrier and peaking amplifiers, a carrier amplifier 14, a peaking amplifier 15, first output matching circuits 16 of the carrier and peaking amplifiers, offset lines 17 of the carrier and peaking amplifiers, a quarter wave circuit (a λ/4 transformer) 18, and a second output matching circuit 19 which connects power amplification apparatuses connected in parallel and outputs a final output power.
The Doherty power amplification apparatus shown in FIG. 1 changes the load impedance of the carrier amplifier 14 using the λ/4 transformer 18 and thereby improves efficiency.
The delay compensation circuit 12 compensates for the delay that has occurred by the λ/4 transformer 18.
The offset lines 17 are to compensate for internal capacitor components of the output terminals of the carrier amplifier 14 and the peaking amplifier 15. The offset lines 17 function to appropriately change the load impedance of the carrier amplifier 14 and prevent current from flowing into the peaking amplifier 15 at a low output power.
In the conventional power amplification apparatus, the efficiency of an output terminal is improved using the output matching circuits, the λ/4 transformer for adjusting output load impedance and the offset lines for perfect load impedance change. However, a problem is caused in that a broadband operation is limited due to the presence of the λ/4 transformer and the offset lines. Also, while the delay compensation circuit for compensating a delay occurring due to the λ/4 transformer is positioned at the input end of the second amplifier, the delay compensation circuit restricts the broadband operation of the power amplification apparatus connected in parallel.